A key component in semiconductor applications is a solid-state switch. As an example, switches turn loads of automotive applications or industrial applications on and off. Solid-state switches typically include, for example, field effect transistors (FETs) like metal-oxide-semiconductor FETs (MOSFETs) or insulated gate bipolar transistors (IGBTs).
In these applications, a damage of a gate dielectric between gate and source of the transistors may be caused by an electrostatic discharge event between a gate contact area and a source contact area of the semiconductor device. To protect the gate dielectric from an electrostatic discharge event, electrostatic discharge (ESD) protection structures are provided, which protect the transistors from electrostatic discharge during assembly or operation, for example. These ESD protection structures require non-negligible area within the integrated semiconductor device.
Furthermore, when providing a symmetrical electrostatic discharge (ESD) protection structure between a gate and source contact structure, an asymmetric robustness of the device in view of the ESD polarity between gate and source leads to restraints in tests of the semiconductor devices.
It is thus desirable to provide a semiconductor device structure with enhanced ESD protection and thermal characteristics, having at the same time an optimized area efficiency.